Recently, as one of the high speed signal processing systems, there has been discussed the achievement of a spectrum analyzer or the like capable of sampling a broadband analog signal to convert the sampled signal into a digital signal sequence, and carrying out a variety of signal processings such as spectrum analyzing at a high speed.
In such a high speed signal processing system, the mere use of an exiting analog-to-digital converter limits high speed processing responsiveness.
Therefore, it is thought to employ a time-interleaved analog-to-digital converter enabling high speed processing equivalently by carrying out analog-to-digital conversion in accordance with a time interleave scheme using a plurality of the existing analog-to-digital converter.
FIG. 23 is a block diagram depicting a basic configuration of a time-interleaved analog-to-digital converter 10 which has been conventionally known.
FIG. 24 is a timing chart showing an operation of the time-interleaved analog-to-digital converter 10 shown in FIG. 23 for the purpose of explanation.
That is, in this conventional time-interleaved analog-to-digital converter 10, an analog input signal x(t) as shown in FIG. 24 (a) is input to an input terminal 10a. 
This analog input signal x(t) is branched to a plurality of N signal paths by a signal divider 11, and then, the respective branched signals are input correspondingly to N analog-to-digital converters 120 to 12N−1 controlled by a sampling control unit 13 described later, whereby the input signals are converted into a plurality of digital signal sequences X0 to XN−1.
The plurality of digital signal sequences X0 to XN−1 each are input to a signal switching device 14 controlled by the sampling control unit 13 described later.
Here, each sampling control unit 13 has N clocks C0 to CN−1 as shown in (b1) to (bN) shown in FIG. 24, the clocks being internally generated, i.e., N sampling clocks C0 to CN−1 which have a cycle Ts and whose phase has been shifted by Ts/N are supplied to N analog-to-digital converters 120 to 12N−1, respectively correspondingly.
In addition, the sampling control unit 13 assigns to the signal switching device 14 a specifying signal ADNUM (0 to N−1) for specifying the analog-to-digital converter that carries out sampling from among the analog-to-digital converters 120 to 12N−1, as shown in FIG. 24(d), the converters being internally generated.
This specifying signal ADNUM (0 to N−1) is provided as a switching signal for sequentially selectively switching a plurality of digital signal sequences X0 to XN−1 in the signal switching device 14, and outputting the switched signal trains to an output terminal 10b. 
Then, analog-to-digital converters 120 to 12N−1 sample input values x(P), x(P+1), x(P+2), . . . of an analog input signal x(t) at a timing at which each of clocks C0 to CN−1 has been received from the sampling control unit 13, and converts the sampled data to digital data X0, P, X1, P+1, X2, P+2, . . . as shown in (c1) to (cN) of FIG. 24.
Each of these sampled data X0, P, X1, P+1, X2, P+2, . . . are output to the signal switching device 14.
The signal switching device 14 sequentially selects the sampled data X0, P, X1, P+1, X2, P+2, . . . output from the analog-to-digital converter 120 to 12N−1 specified by the specifying signal ADNUM from the sampling control unit 13 from among the analog-to-digital converters 120 to 12N−1, and outputs to an output terminal 10b a digital signal sequence Y(n) in which the sampled data are arranged sequentially in order of sampling as shown in FIG. 24(e).
The thus obtained digital signal sequence Y(n) becomes equivalent to that obtained by sampling an input signal x(t) in a cycle Ts′ that is 1/N of a clock cycle Ts.
Therefore, this time-interleaved analog-to-digital converter 10 can carry out high speed sampling while using low speed analog-to-digital converters 120 to 12N−1.
However, in the above-described conventional time-interleaved analog-to-digital converter 10, there is a problem that an error occurs with a result of signal processing of the obtained sample values by a signal processing system.
This problem is caused by the fact that an error occurs with outputs of the analog-to-digital converters 120 to 12N−1 as a result of a difference in distribution characteristics of the signal divider 12 itself or frequency characteristics of a distribution path and a difference in frequency characteristics of the analog-to-digital converters 120 to 12N−1 when the input signal x(t) is input to be divided to the plurality of analog-to-digital converters 120 to 12N−1.
Therefore, in the case where the signal processing system requires high analog-to-digital conversion precision, there is a need for correcting each of the above-described errors in the above-described conventional time-interleaved analog-to-digital converter 10.
For this calibration, a correction processing may be made by obtaining correction information while a calibration signal is input to the above-described time-interleaved analog-to-digital converter 10.
Specifically, in a state in which the calibration signal has been input, the output data is obtained from each analog-to-digital converter, and the obtained data or a processing result relevant to the data is compared, thereby obtaining correction information required to equalize conversion characteristics of each analog-to-digital converter including an input path in advance.
Then, in a state in which a signal targeted for analog-to-digital conversion has been input to the above-described conventional time-interleaved analog-to-digital converter 10, a correction processing is made based on the correction information with respect to an output of each analog-to-digital converter.
In order to carry out such a correction processing, for example, a technique of obtaining information required for calibration is disclosed in patent document 1.
That is, this technique is configured to select by a switch either of a sine wave signal output from a signal generator incorporated in the above-described conventional time-interleaved analog-to-digital converter or an analog signal input from an input terminal and targeted for conversion, so as to enable input to a plurality of analog-to-digital converters.
In addition, in this technique, at the time of calibration, an output signal of a signal generator is input to a plurality of analog-to-digital converters, and information required for calibration is obtained from its output data.
Patent document 1: Jpn. Pat. Appln. KOKAI Publication No. 6-152410